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1 ?2016 integrated device technology, inc. october 28, 2016 general description the 8t49n1012 has one fractional -feedback pll that can be used for frequency synthesis. it is equipped with two integer and eight fractional output dividers, allo wing the generation of up to ten different output frequencies, ranging from 8khz to 1ghz. eight of these frequencies are completely independent of each other and the inputs. two more are related frequencies. the twelve outputs may select among lvpecl, lvds, hscl or lvcmos output levels. this functionality makes it ideal to be used in any frequency synthesis application, including 1g, 10g, 40g and 100g synchronous ethernet, otn, and sonet/sdh, including itu-t g.709 (2009) fec rates. the device supports output enabl e inputs and lock and los status outputs. the device is programmable through an i 2 c interface. it also supports i 2 c master capability to allow th e register configuration to be read from an external eeprom. applications ? otn or sonet / sdh equipment line cards (up to oc-192, and supporting fec ratios) ? gigabit and terabit ip switches / routers ? wireless base station baseband ? data communications features ? <350fs rms typical jitter (incl uding spurs), @122.88mhz (12khz to 20mhz) ? operating modes: locked to input signal and free-run ? operates from a 10mhz to 40mhz fundamental-mode crystal ? accepts one lvpecl, lvds, lvhstl, hcsl or lvcmos input clock ? accepts frequencies ranging from 10mhz up to 600mhz ? clock input monitoring ? generates 12 lvpecl / lvds / hscl or 24 lvcmos output clocks ? output frequencies ranging from 8khz up to 1.0ghz (q[8:11], differential) ? output frequencies ranging from 8khz to 250mhz (lvcmos) ? two output enable control inputs ? lock and loss-of-signal status outputs ? programmable output de-skew adjus tments in steps as small as 16ps ? register programmable through i 2 c or via external i 2 c eeprom ? bypass clock paths and refer ence output for system tests ? power supply modes: ? v cc / v cca / v cco ? 3.3v / 3.3v / 3.3v ? 3.3v / 3.3v / 2.5v ? 3.3v / 3.3v / 1.8v (lvcmos) ? 2.5v / 2.5v / 3.3v ? 2.5v / 2.5v / 2.5v ? 2.5v / 2.5v / 1.8v (lvcmos) ? -40c to 85c ambient operating temperature ? package: 72qfn, lead-free rohs (6) 8t49n1012 datasheet femtoclock ? ng 12-output ? frequency synthesizer
2 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 8t49n1012 block diagram fracn div a fractional feedback pll status registers pll_byp control registers lock osc osci 1, 2, 4, x2 clk otp i 2 c master i 2 c slave reset logic sclk sdata serial eeprom q0 nclk osco clk_sel ref_out los q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 fracn div b fracn div c fracn div d fracn div e fracn div f fracn div g fracn div h intn div i intn div j nrst 0 1 oe[1:0] sa1 figure 1. 8t49n1012 functional block diagram
8xxxxxx 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 clk nclk clk_sel v cccs v cca v cca v cca cap cap_ref v cca los v cco4 q4 nq4 nrst v cco5 q5 nq5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 rsvd ref_out v cca osci osco lock v cco10 q11 nq11 q10 nq10 nc v cco8 q9 nq9 q8 nq8 rsvd 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 pll_byp nc q0 nq0 v cco0 v cco1 q1 nq1 nc rsvd nc v cco2 q2 nq2 nc v cco3 q3 nq3 sa1 v ccd sclk sdata v ee v cc nc nc v cco7 q7 nq7 nc oe0 nc q6 nq6 v cco6 oe1 3 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet pin assignment for 72-pin, 10mm x 10mm vfqfn package figure 2. pinout drawing
4 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet pin description and pin characteristic tables table 1. pin descriptions 1 number name type description 1 ref_out output single-ended ref output. 1.8v lv cmos/lvttl interface levels. 2 v cca power core analog functions supply pin. 3 osci input crystal input. accepts a 10mhz-40mhz re ference from a clock oscillator or a 12pf fundamental mode, parallel-resonant crystal. 4 osco output crystal output. this pin should be connected to a crystal. if an oscillator is connected to osci, then this pin must be left unconnected. 5 lock output pll lock indicator. lvcmos/lvttl interface levels. 6 v cco10 power output supply for q10 and q11 output clock pairs. 7 q11 output output clock 11. refer to the output drivers section for more details. 8 nq11 output output clock 11. refer to the output drivers section for more details. 9 q10 output output clock 10. refer to the output drivers section for more details. 10 nq10 output output clock 10. refer to the output drivers section for more details. 11 nc unused no internal connection. 12 rsvd reserved reserved - leave unconnected. 13 v cco8 power output supply for q8 and q9 output clock pairs. 14 q9 output output clock 9. refer to the output drivers section for more details. 15 nq9 output output clock 9. refer to the output drivers section for more details. 16 q8 output output clock 8. refer to the output drivers section for more details. 17 nq8 output output clock 8. refer to the output drivers section for more details. 18 rsvd reserved reserved - leave unconnected. 19 sa1 input pulldown i 2 c lower address bit a1. 20 v ccd power core digital functions supply voltage. 21 sclk i/o pullup i 2 c interface bi-directional clock. 22 sdata i/o pullup i 2 c interface bi-directional data. 23 v ee power negative supply voltage. 24 v cc power core functions supply voltage. 25 nc unused no internal connection. 26 nc unused no internal connection. 27 v cco7 power output supply for q7 output clock pair. 28 q7 output output clock 7. refer to the output drivers section for more details. 29 nq7 output output clock 7. refer to the output drivers section for more details. 30 nc unused no internal connect. 31 oe0 input pulldown output enable. lvcmos/l vttl interface levels. 32 nc unused no internal connection. 33 q6 output output clock 6. refer to the output drivers section for more details. 34 nq6 output output clock 6. refer to the output drivers section for more details. 35 v cco6 power output supply for q6 output clock pair. 36 oe1 input pulldown output enable. lvcmos/lvttl interface levels. 37 nq3 output output clock 3. refer to the output drivers section for more details. 38 q3 output output clock 3. refer to the output drivers section for more details.
5 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 39 v cco3 power output supply for q3 output clock pair. 40 nc unused no internal connection. 41 nq2 output output clock 2. refer to the output drivers section for more details. 42 q2 output output clock 2. refer to the output drivers section for more details. 43 v cco2 power output supply for q2 output clock pair. 44 nc unused no internal connection. 45 rsvd reserved pulldown reserved - leave unconnected. 46 nc unused no internal connection. 47 nq1 output output clock 1. refer to the output drivers section for more details. 48 q1 output output clock 1. refer to the output drivers section for more details. 49 v cco1 power output supply for q1 output clock pair. 50 v cco0 power output supply for q0 output clock pair. 51 nq0 output output clock 0. refer to the output drivers section for more details. 52 q0 output output clock 0. refer to the output drivers section for more details. 53 nc unused no internal connection. 54 pll_byp input pulldown bypass selection. allow pll references to bypass pll and appear at q[0:3]. lvttl / lvcmos interface levels. 55 nq5 output output clock 5. refer to the output drivers section for more details. 56 q5 output output clock 5. refer to the output drivers section for more details. 57 v cco5 power output supply for q5 output clock pair. 58 nrst input pullup master reset input. lvttl / lvcmos interface levels. 0 = all registers and state machines are reset to their default values 1 = device runs normally 59 nq4 output output clock 4. refer to the output drivers section for more details. 60 q4 output output clock 4. refer to the output drivers section for more details. 61 v cco4 power output supply for q4 output clock pair. 62 los output loss of reference to pll indicator. lvcmos/lvttl interface levels. 63 v cca power core analog function supply voltage. 64 cap_ref analog pll external capacitance reference. 65 cap analog pll external capacitance. a 0.1f capacitance value across cap and cap_ref pins is recommended. 66 v cca power core analog function supply voltage. 67 v cca power core analog function supply voltage. 68 v cca power core analog function supply voltage. 69 v cccs power supply voltage for st atus and control signals: nrst, lock, los, pll_byp, oe[1:0]. 70 clk_sel input pullup clock select pin: ? 0: clk, nclk ? 1: xtal (default) table 1. pin descriptions 1 (continued) number name type description
6 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 71 nclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v cc /2. 72 clk input pulldown non-inverting differential clock input. epad v ee_ep power exposed pad of package. all ground pi ns and epad must be connected before any positive supply voltage is applied. note 1. pullup and pulldown refer to internal input resistors. see ta ble 2 , pin characteristics, for typical values. table 2. pin characteristics 1 note 1. v ccox denotes: v cco0 through v cco8, v cco10. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 note 2. this specification does no t apply to osci and osco pins. 3.5 pf r pullup internal pullup resistor 51 k ? r pulldown internal pulldown resistor 51 k ? c pd power dissipation capacitance (per output pair) lvcmos; q[0:7] v ccox = 3.465v 17 pf lvcmos; q[8:11] v ccox = 3.465v 14 pf lvcmos; q[0:7] v ccox = 2.625v 15 pf lvcmos; q[8:11] v ccox = 2.625v 13 pf lvcmos; [0:7] v ccox = 1.89v 15 pf lvcmos; q[8:11] v ccox = 1.89v 11.5 pf lvds, hscl, lvpecl or hi-z; q[0:7] v ccox = 3.465v or 2.625v 4.5 pf lvds, hscl, lvpecl or hi-z; q[8:11] v ccox = 3.465v or 2.625v 2.5 pf r out output ? impedance lock, los v cccs = 3.3v 43 ? v cccs = 2.5v 52 ? q[0:11], nq[0:11] lvcmos operation selected 22 ? ref_out 30 ? table 1. pin descriptions 1 (continued) number name type description
7 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet principles of operation the 8t49n1012 accepts either a crys tal input or a differential input clock. it generates up to twelve ou tput clocks ranging from 8khz up to 1.0ghz. the 8t49n1012 has one fractional-feedback pll that tracks either a crystal or input reference clock. from the output of the pll a wide range of output frequencies can be simultaneously generated. the device monitors the input clock and generates an alarm when an input clock or crystal failure is detected. the pll provides a frequency referenc e that is unrelated to the input clock or crystal frequency. the pll frequency may be used by any of eight fractional output dividers or two integer output dividers to generate up to 10 different frequencies on the twelve outputs. the device supports programmable skew adjustment on the eight fractional output dividers. the device is programmable through an i 2 c interface and may also autonomously read its register sett ings from an internal one-time programmable (otp) memory or an external serial i 2 c eeprom. bypass path and reference output for system test purposes, th e pll may be bypassed. when pll_byp is asserted the pll input reference will be presented on the q0 - q3 outputs. note that th is frequency represents the selected input frequency after the pre-scaler circuit. additionally, the input reference clock or crystal frequency may be enabled on the ref_out pin. this is the selected input frequency before the pre-scaler circuit. no te that since ref_out is an lvcmos output, it is limited to ? 250mhz. if the selected input frequency is higher than this, ref_out must be disabled. input clock selection and pre-scaling the 8t49n1012 is referenced either to a fundamental mode crystal in the range of 10mhz to 40mhz or to an input reference clock with frequency ranging from 10mhz up to 600mhz. the reference clock input can accept lvpecl, lvds, lvhstl, hcsl or lvcmos inputs using 1.8v, 2.5v or 3.3v logic leve ls. to use lvcmos inputs, please refer to the application note later in this datasheet, wiring the differential input to a ccept single-ended levels (page 37) for biasing instructions. the input reference clock does not support transmission of spread-spectrum clocking sources. si nce this family is intended for high-performance applications, it will assume input reference sources to have stabilities of + 100ppm or better. the user selects via the clk_sel input pin whether the crystal (clk_sel = high) or the clk/nclk (clk_sel = low) is used as the reference frequency. the clk_sel input has an internal pull-up so that if it is not co nnected, the crystal will be selected as the source. the output of this selection logi c may be monitored via the ref_out pin. whichever source is selected is passed to a pre-scaler function which can multiply that frequency by a factor of 2, pass it on directly or divide it by 2 or by 4. for best performance, this pre-scaler should be set to provide the highest frequency less than the 150mhz limit the pll can accept. this scaled reference may be monitored on the q[0:3] outputs by use of the pll_byp pin or via register control. input clock monitor the pll input (after pre-scaling) is monitored for loss of signal (los). if no activity has been detected by the pll on its input within 64 clock periods then the input is considered to have failed and the internal loss-of-signal status flag is set and the los pin is asserted. once a los on the selected input reference is detected, the internal los alarm will be asserted and it will remain asserted until that pll input clock returns. note that the internal los alarm regi ster bit is ?sticky?. once asserted it will remain asserted until a ?1? has been written to that register bit to clear it. if the los condition is still in effect when the ?sticky? bit is cleared, then it will immediately re-assert. the los pin is not ?sticky? and will directly reflect the current los status of the selected input reference. loop bandwidth & lock indication the 8t49n1012 has a fixed loop bandwidth set using internal components of approximately 200khz. once the pll has locked to the selected input reference, then the internal lock status will be set. the internal lock status will be reflected directly on the lock pin and on the internal lock status register. note that the internal lock status register bit is ?sticky?. once asserted it will remain asserted unt il a ?1? has been written to that register bit to clear it. if the lock condition is still in effect when the ?sticky? bit is cleared, then it will immediately re-assert.
8 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet fractional output divi ders (div a - div h) for the fractional output dividers, th e output divide ratio is given by: output divide ratio = (n.f)x2 n = integer part: 4, 5, ...(2 18 -1) f = fractional part: [0, 1, 2, ...(2 28 -1)]/(2 28 ) for integer operation (f = 0) of th ese fractional output dividers, n = 3 is also supported. the max freq uency with integer divider mode is 667.67mhz, and with fractional divider mode is 400mhz. integer output divide rs (div i & div j) each integer output divider block consists of two divider stages in a series to achieve the desired total ou tput divider ratio. the first stage divider may be set to divide by 4, 5 or 6. the second stage of the divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. the total divide ratios, settings and possible output frequencies are shown in table 3 . table 3. integer output divider ratios output skew adjustme nt (div a - div h) for the fractional output dividers div a through div h, the user may apply adjustments that are proporti onal to the period of the clock source driving each output divi der. the phase of those divider outputs may be adjusted with a gr anularity of 1/16th of the vco period. for example a 4ghz vco frequency gives a granularity of 16ps. anywhere from 0 to 15 steps of skew adjustment can be added to the output clock from each fractional output divider. this is performed by directly writing the required offset (from the nominal rising edge position) in units of 1/16 th of the output period into a register. then the pll_syn bit must be toggled to load the new value. the output will then jump directly to that new offset value. for this reason, this adjustment should be made as the output is initially programmed or in high-impedance. output buffers the q0 to q11 clock outputs are provided with register-controlled output buffers. by selecting the out put drive type in the appropriate register, any of these outputs can support lvcmos, lvpecl, hscl or lvds logic levels. the operating voltage ranges of each output is determined by its independent output power pin (v cco ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential oper ation and lvcmos operation. in addition, lvcmos output operation supports 1.8v v cco . each output may be enabled or disabled by register bits and/or oe[1:0] pins. when disabled an output will be in a high impedance state. each output has the capability of being inverted (180 degree phase shift). lvcmos operation when a given output is configured to provide lvcmos levels, then both the q and nq outputs will toggle at the selected output frequency. all the previously described configuration and control apply equally to both outputs. frequency, skew adjustment, voltage levels and enable / disable status apply to both the q and nq pins. when configured as lvcmos, the q and nq outputs can be selected to be phase-aligned with each other or inverted relative to one another. phase-aligned outputs will have increased simultaneous switching currents which can neg atively affect phase noise performance and power consumption. it is recommended that use of this selection be kept to a minimum. output enables control of output enable for all outputs may be performed either via pin control or via register control as dictated by the oemode control bit. if oemode = 0, then the oe[1:0] pins will control the output buffers as indicated in table 4 . if oemode = 1, then the outen regi ster bits will control the function of each output buffer individually. table 4. output enable pin functions 1st-stage divide 2nd-stage divide total divide minimum f out mhz maximum f out mhz 4 1 4 750 1000 515600800 6 1 6 500 666.7 428375500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051 oe1 oe0 description 0 0 all outputs disabled (high-impedance) 0 1 q[0:3] enabled; q[4:11] disabled 1 0 q[0:3] disabled; q[4:11] enabled 1 1 all outputs enabled
9 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet power-saving modes to allow the device to consume the least power possible for a given application, the device is divided into several power domains each with its own independent supply pins. some of the power domains may be powered-down under register control. note that if the register control is used to disable a power domain, the associated power pin must still have an appropriate voltage applied. each power domain may be powered with one of the indi cated voltages regardless of what voltage is provided to any other domain. please refer to the power calculation section near the end of this document for details on power consumption in a specific configuration. table 5. device power domains device hardware configuration the 8t49n1012 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with one complete device configuration. if the device is set to read a configuration from an external, serial eeprom, then the values read will overwrite the otp-defined values. this configuration can be over-writt en using the serial interface once device initialization is complete. any configuration written via the programming interface needs to be re-written after any power cycle or reset. please contact idt if a specific factory-programmed configuration is desired. device start-up & reset behavior the 8t49n1012 has an internal power-up reset (por) circuit and a master reset input pin nr st. if either is asserted, the device will be in the reset state. for highly programmable devices, it's common practice to reset the device immediately after the initial power-on sequence. idt recommends connecting the nrst input pin to a programmable logic source for optimal functionality. it is recommended that a minimum pulse width of 10ns be used to drive the nrst input pin. while in the reset state (nrst input asserted or por active), the device will operate as follows: ? all registers will return to & be held in their default states as indicated in the applicable register description. ? all internal state machines wi ll be in their reset conditions. ? the serial interface will not respond to read or write cycles. ? all clock outputs will be disabled. ? all alarm status bits will be cleared. upon the latter of the internal por circuit expiring or the nrst input negating, the device will exit re set and begin self-configuration. the device will load an initial block of its internal registers using the configuration stored in the inter nal one-time programmable (otp) memory. once this step is complete, the 8t49n1012 will check the register settings to see if it should load the remainder of its configuration from an external i 2 c eeprom at a defined address or continue loading from otp. see the section on i 2 c boot initialization for details on how this is performed. once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the pll to the selected source and begin operation. once the pll is locked, all the output dividers will be synchronized and output skew adjustments can then be applied if desired. power pin supported voltages power-down mode functions in the domain v cc 2.5v, 3.3v not supported otp v ccd 2.5v, 3.3v not supported internal registers v cca 2.5v, 3.3v not supported input clock, crystal a nd input reference logic, pre-scaler, pll v cccs 1.8v, 2.5v, 3.3v not supported output / input buffers for pins: nrst, clk_sel, pll_ byp, lock, los, oe[1:0], sa1, sclk and sdata v cco0 1.8v 1 , 2.5v, 3.3v note 1. operation of 1.8v is only s upported when in lvcmos output mode. supported div a, q0 output buffer & mux v cco1 1.8v 1 , 2.5v, 3.3v supported div b, q1 output buffer & mux v cco2 1.8v 1 , 2.5v, 3.3v supported div c, q2 output buffer & mux v cco3 1.8v 1 , 2.5v, 3.3v supported div d, q3 output buffer & mux v cco4 1.8v 1 , 2.5v, 3.3v supported div e, q4 output buffer & mux v cco5 1.8v 1 , 2.5v, 3.3v supported div f, q5 output buffer & mux v cco6 1.8v 1 , 2.5v, 3.3v supported div g, q6 output buffer & mux v cco7 1.8v 1 , 2.5v, 3.3v supported div h, q7 output buffer & mux v cco8 1.8v 1 , 2.5v, 3.3v supported div i, q8 & q9 output buffers & muxes v cco10 1.8v 1 , 2.5v, 3.3v supported div j, q 10 & q11 output buffers & muxes
10 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration, to allow access to any of the internal registers for device programming or examination of internal status. all registers are configured to have default values. see the specifics for each register for details. the device has the additional capab ili ty of becoming a master on the i 2 c bus only for the purpose of reading its initial register configurations from a serial eeprom on the i 2 c bus. writing of the configuration to the serial eeprom must be performed by another device on the same i 2 c bus or pre-programmed into the device prior to assembly. i 2 c mode operation the i 2 c interface is designed to fully support v1.2 of the i 2 c specification for normal and fast mode operation. the device acts as a slave device on the i 2 c bus at 100khz or 400khz using the address defined in the serial interface control register (0006h), as modified by the sa1 input pin settings. the interface accepts byte-oriented block write and bl ock read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at which point, all data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 51k : typical. current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data? n a p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n a p offset ? addr ? msb a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master offset ? addr ? lsb a offset ? addr ? msb a offset ? addr ? lsb a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge a= ? none ? acknowledge p ? = ? stop figure 3. i 2 c slave read and write cycle sequencing
11 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet i 2 c master mode when operating in i 2 c mode, the 8t49n1012 has the capability to become a bus master on the i 2 c bus for the purposes of reading its configuration from an external i 2 c eeprom. only a block read cycle will be supported. as an i 2 c bus master, the 8t49n1012 will support the following functions: ? 7-bit addressing mode ? base address register for eeprom ? validation of the read block via ccitt-8 crc check against value stored in last byte (b4h) of eeprom ? support for 100khz and 400khz operation with speed negotiation. if bit d0 is set at byte address 05h in the eeprom, this will shift from 100khz operation to 400khz operation. ? support for 1- or 2-byte addressing mode ? master arbitration with prog rammable number of retries ? fixed-period cycle response timer to prevent permanently hanging the i 2 c bus. ? read will abort with an alarm (bootf ail) if any of the following conditions occur: slave nack, arbitration fail, collision during address phase, crc failure, slave response time-out the 8t49n1012 will not support the following functions: ?i 2 c general call ? slave clock stretching ?i 2 c start byte protocol ? eeprom chaining ? cbus compatibility ? responding to its own slave address when acting as a master ? writing to external i 2 c devices including the external eeprom used for booting figure 4. i 2 c master read cycle sequencing sequential read (1 r byte offset address) s dev addr + w a data 0 a data 1 a a data n a p sr dev addr + r a offset addr a sequential read (2 r byte offset address) s dev addr + w a data 0 a data 1 a a data n a p offset addr msb a sr dev addr + r a offset addr lsb a from master to slave from slave to master s = start sr = repeated start a = acknowledge a= none acknowledge p = stop
12 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet i 2 c boot-up initialization mode if enabled (via the boot_eep bit in the startup register), once the nrst input has been deasserted (high) and its internal power-up reset sequence has completed, the device will contend for ownership of the i 2 c bus to read its initial register settings from a memory location on the i 2 c bus. the address of that memory location is kept in non-volatile memory in the st artup register. during the boot-up process, the device will not respond to serial control port accesses. once the initialization process is co mplete, the contents of any of the device?s registers can be altered. it is the responsibility of the user to make any desired adjustments in initial values directly in the serial bus memory. if a nack is received to any of the read cycles performed by the device during the initialization proc ess, or if the crc does not match the one stored in a ddress b4h of the eeprom the process will be aborted and any uninitialized registers will remain with their default values. the bootfail bit (0214h) in the global status register will also be set in this event. contents of the eeprom should be as shown in table 6 . table 6. external se rial eeprom contents eeprom offset (hex) contents d7 d6 d5 d4 d3 d2 d1 d0 00 1111111 1 01 1111111 1 02 1111111 1 03 1111111 1 04 1111111 1 05 1111111 serial eeprom speed select 0 = 100khz 1 = 400khz 06 1 8t49n1012 device i 2 c address [6:2] 1 1 07 0000000 0 08 - b3 desired contents of device registers 08h - b3 b4 serial eeprom crc b5 - ff unused
13 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet register descriptions table 7a. register blocks table 7b. startup control register bit field locations and descriptions register ranges offset (hex) register block description 0000 - 0001 startup control registers 0002 - 0005 device id control registers 0006 - 0007 serial interface control registers 0008 - 0032 reserved 0033 - 003e pll divider control registers 003f - 0048 output buffer control registers 0049 - 008c output divider control registers 008d - 008f output mux control registers 0090- 0091 divider power control registers 0092 - 0099 reserved 009a - 009f pll control registers 00a0- 00a2 buffer power control registers 00a3 - 01ff reserved 0200 - 0203 interrupt status registers 0204- 0212 reserved 0213 - 0215 global status registers 0216 - 03ff reserved startup control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0000 eep_rty[4:0] rsvd nboot_otp nboot_eep 0001 eep_a15 eep_addr[6:0] startup control register block field descriptions bit field name field type default value description eep_rty[4:0] r/w 00001b select number of times arbitration for the i 2 c bus to read the serial eeprom will be retried before being aborted. note that this number does not include the original try. nboot_otp r/w various 1 note 1. these values are specific to the device config uration and can be customized wh en ordering. refer to the femtoclock ng uni- versal frequency translator ordering product information guide or custom datasheet addendum for more details. internal one-time programmable (otp) memory usage on power-up: 0 = load power-up configuration from otp 1 = only load 1st eight bytes from otp nboot_eep r/w various 1 external eeprom usage on power-up: 0 = load power-up configurat ion from external serial eeprom (overwrites otp values) 1 = don?t use external eeprom eep_a15 r/w various 1 serial eeprom supports 15-bit addressing mode (multiple pages). eep_addr[6:0] r/w various 1 i 2 c base address for serial eeprom. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
14 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7c. device id control register bit field locations and descriptions note 1:these values are specific to the device configur ation and can be customized when ordering. refer to the femtoclock ng uni - versal frequency translator ordering product information guide or custom datasheet addendum for more details. table 7d. serial interface control regi ster bit field locations and descriptions device id register contro l block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0002 rev_id[3:0] dev_id[15:12] 0003 dev_id[11:4] 0004 dev_id[3:0] dash_code[10:7] 0005 dash_code[6:0] 1 device id control register block field descriptions bit field name field type default value description rev_id[3:0] r/w 0000b device revision. dev_id[15:0] r/w 060eh device id code. dash_code [10:0] r/w various 1 device dash code. decimal value assigned by idt to identify the configuration loaded at the factory. may be over-written by users at any time. refer to femtoclock ng universal frequency translator ordering product information to identify major configuration parameters associated with this dash code value. serial interface control block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0006 rsvd devadd[6:2] devadd[1] rsvd 0007 rsvd 1 serial interface control regist er block field descriptions bit field name field type default value description devdd[6:2] r/w various 1 note 1. these values are specific to t he device configuration and can be customized when ordering. generic dash codes -900 thro ugh -903, -998 and -999 are available and programmed with the default i 2 c address of 1111100b.please refer to the femtoclock ng universal frequency translator ordering product information guide or custom datasheet addendum for more details. configurable portion of i 2 c base address (bits 6: 2) for this device. devadd[1] r/o 0b i 2 c base address bit 1. this ad dress bit reflects the status of the sa1 external input pin. see pin description and pin characteristic tables (page 4). rsvd r/o 0b reserved. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
15 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7e. pll divider control register bit field locations and descriptions pll divider control register block field locations address (hex)d7d6d5d4d3d2d1 d0 0033 rsvd dsm_int[8] 0034 dsm_int[7:0] 0035 dsmfrac[23:16] 0036 dsmfrac[15:8] 0037 dsmfrac[7:0] 0038 rsvd 0039 01h 003a rsvd 003b rsvd 003c dsm_ord[1:0] dcxogain[1:0] rsvd dithgain[2:0] 003d rsvd 003e rsvd pll divider control register block field descriptions bit field name field type default value description dsm_int[8:0] r/w 02dh integer portion of the delta-sigma modulator value. dsmfrac[23:0] r/w 000000h fractional portion of delta-sigma modulator value. divide this number by 2 24 to determine the actual fraction. dsm_ord[1:0] r/w 11b delta-sigma modulator order for pll: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation dcxogain[1:0] r/w 01b multiplier applied to instantaneous frequency error before it is applied to the digitally controlled oscillator: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain[2:0] r/w 000b dither gain setting for digitally controlled oscillator: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
16 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7f. output buffer control regist er bit field locations and descriptions output buffer control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 003f rsvd oemode outen[11:8] 0040 outen[7:0] 0041 rsvd pol_q[11:8] 0042 pol_q[7:0] 0043 outmode11[2:0] se_mode11 outmode10[2:0] se_mode10 0044 outmode9[2:0] se_mode9 outmode8[2:0] se_mode8 0045 outmode7[2:0] se_mode7 outmode6[2:0] se_mode6 0046 outmode5[2:0] se_mode5 outmode4[2:0] se_mode4 0047 outmode3[2:0] se_mode3 outmode2[2:0] se_mode2 0048 outmode1[2:0] se_mode1 outmode0[2:0] se_mode0 output buffer control register block field descriptions bit field name field type default value description oemode r/w 0b register or oe[1:0] pins to control output enable operation: 0 = oe[1:0] pins will control enabling of the output buffers as shown in table 4 1 = oe[1:0] pins are disabled and output en ables are controlled by internal registers outen[11:0] r/w fffh output enable control for clo ck outputs q[0:11], nq[0:11]: 0 = qn is in a high-impedance state 1 = qn is enabled as indicated in appropriate outmoden[2:0] register field pol_q[11:0] r/w 000h polarity of clock out puts q[0:11], nq[0:11]: 0 = normal polarity 1 = inverted polarity outmodem [2:0] r/w 001b output driver mode of operation for clock output pair qm, nqm: 000 = high-impedance 001 = lvpecl 010 = lvds 011 = lvcmos 100 = hcsl 101 - 111 = reserved se_modem r/w 0b behavior of output pair qm, nqm when lvcmos operation is selected ? (must be 0 if lvds, hcsl or lvpec l output style is selected): 0 = qm and nqm are both the same frequency but inverted in phase 1 = qm and nqm are both the same frequency and phase
17 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7g. output divider control regist er bit field locations and descriptions output divider control regi ster block field locations address (hex)d7d6d5d4d3d2d1d0 0049 rsvd n_diva[17] n_diva[16] 004a n_diva[15:8] 004b n_diva[7:0] 004c rsvd n_divb[17] n_divb[16] 004d n_divb[15:8] 004e n_divb[7:0] 004f rsvd n_divc[17] n_divc[16] 0050 n_divc[15:8] 0051 n_divc[7:0] 0052 rsvd n_divd[17] n_divd[16] 0053 n_divd[15:8] 0054 n_divd[7:0] 0055 rsvd n_dive[17] n_dive[16] 0056 n_dive[15:8] 0057 n_dive[7:0] 0058 rsvd n_divf[17] n_divf[16] 0059 n_divf[15:8] 005a n_divf[7:0] 005b rsvd n_divg[17] n_divg[16] 005c n_divg[15:8] 005d n_divg[7:0] 005e rsvd n_divh[17] n_divh[16] 005f n_divh[15:8] 0060 n_divh[7:0] 0061 rsvd n1_divi[1:0] 0062 n2_divi[15:8] 0063 n2_divi[7:0] 0064 rsvd n1_divj[1:0] 0065 n2_divj[15:8] 0066 n2_divj[7:0] 0067 rsvd f_diva[27:24] 0068 f_diva[23:16] 0069 f_diva[15:8] 006a f_diva[7:0] 006b rsvd f_divb[27:24] 006c f_divb[23:16] 006d f_divb[15:8] 006e f_divb[7:0] 006f rsvd f_divc[27:24] 0070 f_divc[23:16] 0071 f_divc[15:8]
18 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 0072 f_divc[7:0] 0073 rsvd f_divd[27:24] 0074 f_divd[23:16] 0075 f_divd[15:8] 0076 f_divd[7:0] 0077 rsvd f_dive[27:24] 0078 f_dive[23:16] 0079 f_dive[15:8] 007a f_dive[7:0] 007b rsvd f_divf[27:24] 007c f_divf[23:16] 007d f_divf[15:8] 007e f_divf[7:0] 007f rsvd f_divg[27:24] 0080 f_divg[23:16] 0081 f_divg[15:8] 0082 f_divg[7:0] 0083 rsvd f_divh[27:24] 0084 f_divh[23:16] 0085 f_divh[15:8] 0086 f_divh[7:0] 0087 fine_c[3:0] fine_a[3:0] 0088 fine_d[3:0] fine_b[3:0] 0089 fine_g[3:0] fine_e[3:0] 008a fine_h[3:0] fine_f[3:0] 008b rsvd 008c rsvd output divider control register block field descriptions bit field name field type default value description n1_divm[1:0] r/w 10b 1st stage output divider ratio fo r integer output dividers i and j: ? 00 = /5 01 = /6 10 = /4 11 = output qm, nqm not switching n2_divm[15:0] r/w 0002h 2nd stage output divider ratio fo r integer output dividers i and j: actual divider ratio is 2x the value written here. ? a value of 0 in this register will by pass the second stage of the divider. n_divm[17:0] r/w 00008h integer portion of output divider rati o for fractional output dividers a - h: values of 0, 1 or 2 cannot be written to th is register. actual integer portion is 2x the value written here. output divider control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0
19 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7h. output mux control register bit field locations and descriptions f_divm[27:0] r/w 0000000h fractional portion of output divider ratio for fractional output dividers a - h: actual fractional portion is 2x the value written here. ? fraction = (f_divm * 2) * 2 -28 fine_m[3:0] r/w 0100b number of 1/16ths of the vco clock period to add to the phase of a fractional output divider a-h. the pll_syn bit must be t oggled to make this value take effect. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. output divider control regist er block field descriptions bit field name field type default value description output mux control regist er block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 008d rsvd pll_syn 008e rsvd mux_10_11 mux_8_9 008f mux_7 mux_6 mux_5 mux_4 mux_3 mux_2 mux_1 rsvd output mux control register block field descriptions bit field name field type default value description pll_syn r/w 0b output synchronization control. setting this bit from 0 ? 1 will cause the output divider(s) to be held in reset. setting this bit from 1 ? 0 will release all the output divider(s) to run from the same point in time with the outpu t skew adjustment reset to 0. mux_10_11 r/w 0b output divider selection for ou tput q10, nq10 and q11, nq11: 0 = output of integer divider j is used 1 = output of integer divider i is used mux_8_9 r/w 0b output divider selection for output q8, nq8 and q9, nq9: 0 = output of integer divider i is used 1 = output of integer divider j is used mux_7 r/w 0b output divider selection for output q7, nq7: 0 = output of fractional divider h is used 1 = output of fractional divider g is used mux_6 r/w 0b output divider selection for output q6, nq6: 0 = output of fractional divider g is used 1 = output of fractional divider h is used mux_5 r/w 0b output divider selection for output q5, nq5: 0 = output of fractional divider f is used 1 = output of fractional divider e is used mux_4 r/w 0b output divider selection for output q4, nq4: 0 = output of fractional divider e is used 1 = output of fractional divider f is used mux_3 r/w 0b output divider selection for output q3, nq3: 0 = output of fractional divider d is used 1 = output of fractional divider a is used mux_2 r/w 0b output divider selection for output q2, nq2: 0 = output of fractional divider c is used 1 = output of fractional divider a is used mux_1 r/w 0b output divider selection for output q1, nq1: 0 = output of fractional divider b is used 1 = output of fractional divider a is used rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
20 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7i. divider power control register bit field locations and descriptions divider power control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0090 rsvd pwr_divj pwr_divi 0091 pwr_divh pwr_divg pwr_divf pwr_di ve pwr_divd pwr_divc pwr_divb pwr_diva divider power control register block field descriptions bit field name field type default value description pwr_divm r/w 0b power-down control for output divider m: 0 = output divider m operating normally 1 = output divider m powered-down rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
21 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7j. pll control register bi t field locations and descriptions please contact idt through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. pll control register block field locations 009a cpset[2:0] rs[1:0] cp[1:0] wpost 009b rsvd rsvd rsvd rsvd dlcnt dbitm 009c rsvd vcoman dbit1[4:0] 009d rsvd dbit2[4:0] 009e rsvd pll_byp rsvd ref_oe p_mode[1:0] 009f rsvd address (hex) d7 d6 d5 d4 d3 d2 d1 d0 pll control register block field descriptions bit fie ld name field type default value description cpset[2:0] r/w 100b charge pump current setting for pll: 000 = 110a 001 = 220a 010 = 330a 011 = 440a 100 = 550a 101 = 660a 110 = 770a 111 = 880a rs[1:0] r/w 01b internal loop filter series resistor setting for pll: 00 = 330 : 01 = 640 : 10 = 1.2k : 11 = 1.79k : cp[1:0] r/w 01b internal loop filter parallel capacitor setting for pll: 00 = 40pf 01 = 80pf 10 = 140pf 11 = 200pf wpost r/w 1b internal loop filter 2nd pole setting for pll: 0 = rpost = 497 : , cpo st = 40pf 1 = rpost = 1.58k : , c post = 40pf dlcnt r/w 1b digital lock count setting for pll. set to 0 if external capacitor (cap) for pll is >95 nf, otherwise set to 1: 0 = 1 ppm accuracy 1 = 16 ppm accuracy dbitm r/w 0b digital lock manual override setting for pll: 0 = automatic mode 1 = manual mode vcoman r/w 1b manual lock mode vco selection setting for pll: 0 = vco2 1 = vco1 dbit1[4:0] r/w 01011b manual mode digital lock control setting for vco1 in pll. dbit2[4:0] r/w 00000b manual mode digital lock control setting for vco2 in pll. pll_byp r/w 0b pll bypass mode (same function as pll_byp pin): 0 = q[0:3]outputs ope rate normally 1 = q[0:3] outputs driven by pll inp ut reference clock
22 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet ref_oe r/w 0b enable reference output pin: 0 = ref_out pin is high-impedance 1 = ref_out pin is driven from the input reference mux with either the direct crystal frequency or the direct clk input reference frequency (as controlled by the clk_sel pin) p_mode[1:0] r/w 11b pre-scaler mode selection: 00 = selected reference input is driven directly to the pll (divide-by-1) 01 = selected reference input is divided-by-2 before being driven to the pll 10 = selected reference input is divided-by-4 before being driven to the pll 11 = selected reference input is multiplied-by-2 before being driven to the pll rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. pll control register block field descriptions bit field name field type default value description
table 7k. buffer power control register bit field locations and descriptions the power controls below will disable specific logic blocks by turning-off the regulators associ ated with those logic blocks. t he associated power supply pin must remain powered, but minimal current will be drawn. the user must ensure that appropriate control bits are set elsewhere to ensure the powered-down functions are not sele cted to drive other, st ill enabled, output paths. buffer power control register block field locations 00a0 pathh_off pathg_off pathf_off pathe_off pathd_off pathc_off pathb_off patha_off 00a1 rsvd ref_off rsvd pathj_off pathi_off 00a2 rsvd rsvd dsm_off rsvd address (h ex) d7 d6 d5 d4 d3 d2 d1 d0 buffer power control register block field descriptions bi t field name field type default value description pathh_off r/w 0b power control for div h, q7, nq7 output bu ffer and associ ated output mux (associated supply pin: v cco7 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathg_off r/w 0b power control for div g, q6, nq 6 output buffer and associ ated output mux (associated supply pin: v cco6 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathf_off r/w 0b power control for div f, q5, nq 5 output buffer and associ ated output mux (associated supply pin: v cco5 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathe_off r/w 0b power control for div e, q4 , nq4 output buffer and associated output mux (associated supply pin: v cco4 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathd_off r/w 0b power control for div d, q3, nq3 output bu ffer and associ ated output mux (associated supply pin: v cco3 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathc_off r/w 0b power control for div c, q2, nq2 output bu ffer and associ ated output mux (associated supply pin: v cco2 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathb_off r/w 0b power control for div b, q1 , nq1 output buffer and associated output mux (associated supply pin: v cco1 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down patha_off r/w 0b power control for div a, q0 , nq0 output buffer and associated output mux (associated supply pin: v cco0 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathi_off r/w 0b power control for div i, q8, nq8 output buffe r, q9 , nq9 output buffer and associated output mux (associated supply pin: v cco8 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down pathj_off r/w 0b power control for div j, q10, nq10 output bu ffer, q11 , nq11 output buffer and associated output mux (associated supply pin: v cco10 ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down
24 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7l. interrupt status register bit field locations and descriptions this register contains? sticky? bits for tracking the status of the various alarms. whenever an alarm occurs, the appropriate i nterrupt status bit will be set. the interrupt status bit will remain asserted even af ter the original alarm goes away . the interrupt status bits r emain asserted until explicitly cleared by a write of a ?1? to the bit over the serial port. this type of functionality is referred to as read / wri te-1-to-clear (r/w1c). note that the alarm pin is not ?sticky? but reflec ts the real-time status of the appropriate alarm. interrupt status register block field locations 0200 rsvd 0201 rsvd lol_int los_int 0202 rsvd rsvd 0203 rsvd lol_int r/w1c 0b interrupt status bit for loss-of-lock on pll: 0 = no loss-of-lock alarm flag on pll has occu rred since the last time this register bit was cleared. 1 = at least one loss-of-lock alarm flag on pll has occurred since th e last time this register bit was cleared. los_int r/w1c 0b interrupt status bit for pll input reference clock: 0 = no loss-of signal (los) alarm has occurred since the last time this register bit was clea red. 1 = at least one los alarm flag has occurred si nce the last time this register bit was cleared. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. ref_off r/w 0b power control for ref_out output buffer (associated supply pin: v cccs ): 0 = regulator enabled & logic operates normally 1 = regulator disabled and logic powered down dsm_off r/w 0b power control for pll fractional feedback divider (associated supply pin: v ccd ): 0 = feedback divider in fractional mode 1 = feedback divider in integer mode; some power savings will be realized rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. buffer power control register blo ck field descriptions bit field name field type default value description address (hex) d7 d6 d5 d4 d3 d2 d1 d0 interrupt status register block field descriptions bit f ield name field type default value description
25 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 7m. global status register bit field locations and descriptions global status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0213 rsvd rsvd 0214 rsvd rsvd rsvd bootfail 0215 rsvd rsvd rsvd rsvd neep_crc rsvd rsvd eepdone global interrupt status register block field descriptions bit field name field type default value description bootfail r/o - reading of serial eeprom failed. once set this bit is only cleared by reset. neep_crc r/o - eeprom crc error (active low): 0 = eeprom was detected and read, but crc check failed - please reset the device via the nrst pin to retry (serial port is locked) 1 = no eeprom crc error eepdone r/o - serial eeprom read cycl e has completed. once set this bit is only cleared by reset. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
26 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditi ons beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condi tions for extended periods may affect product reliability. supply voltage, v ccx 3.63v inputs, v i osci other input 0v to 2v -0.5v to v ccx + 0.5v outputs, v o (q[0:11], nq[0:11]) -0.5v to v ccox + 0.5v outputs, v o (los, lock, ref_out) -0.5v to v cccs + 0.5v outputs, v o (sclk, sdata) -0.5v to v ccd + 0.5v outputs, i o (q[0:11], nq[0:11]) continuous current surge current 40ma 65ma outputs, i o (ref_out, los, lock, sdata, sclk) continuous current surge current 8ma 13ma junction temperature, t j 125qc storage temperature, t stg -65 q c to 150 qc note: v ccx denotes: v ccd, v cc, v cccs. note: v ccox denotes: v cco0 through v cco8 and v cco10. supply voltage characteristics item rating table 8a. power supply characteristics, v ccx 1 = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1. v ccx denotes: v ccd, v cc, v cccs. symbol parameter test conditio ns minimum typical maximum units v ccx 1 core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v i ccx 2 note 2. i ccx denotes the sum of: i ccd, i cc, i cccs. core supply current 18 28 ma i cca analog supply current all functions enabled 3 note 3. ref_out is disabled to high-impedance. 140 170 ma table 8b. power supply characteristics, v ccx 1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1. v ccx denotes: v ccd, v cc, v cccs. symbol parameter test conditions minimum typical maximum units v ccx 1 core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage 2.375 2.5 2.625 v i ccx 2 note 2. i ccx denotes the sum of: i ccd, i cc, i cccs. core supply current 17 26 ma i cca analog supply current all functions enabled 3 note 3. ref_out is disabled to high-impedance. 137 160 ma
27 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 8c. maximum output supply current, v ee = 0v, t a = -40c to 85c 1 , 2 note 1. internal dynamic s witching current at maximum f out is included. note 2. currents per i cco. symbol parameter test conditions v ccox 3 = 3.3v 5% note 3. v ccox denotes: v cco0 through v cco8 and v cco10. v ccox 3 = 2.5v 5% v ccox = 1.8v 5% 3 units lvpec l lvds hcsl lvcmo s lvpec l lvds hcsl lvcmo s lvcmos i cco0 q0, nq0 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco1 q1, nq1 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco2 q2, nq2 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco3 q3, nq3 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco4 q4, nq4 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco5 q5, nq5 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco6 q6, nq6 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco7 q7, nq7 output supply current outputs unloaded 71 81 71 72 58 66 58 56 48 ma i cco8 4 note 4. supply current specifications refe r to two output pairs (q[8:9] or q[10:11]) being driven by one divider (divider i or j). q[8:9], nq[8:9] outputs ? supply current outputs unloaded 67 86 67 72 50 66 50 53 42 ma i cco10 4 q[10:11], nq[10:11] outputs ? supply current outputs unloaded 67 86 67 72 50 66 50 53 42 ma
28 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet dc electrical characteristics table 9a. lvcmos/lvttl control/stat us signals dc char acteristics, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cccs = 3.3v 2 v ccx +0.3 v v cccs = 2.5v 1.7 v ccx +0.3 v v cccs = 1.8v 1.2 v ccx +0.3 v v il input low voltage v cccs = 3.3v -0.3 0.8 v v cccs = 2.5v -0.3 0.7 v v cccs = 1.8v -0.3 0.3 v i ih input high current pll_byp, ? sa1, oe1, oe0 v cccs = v in = 3.465v or 2.625v or 1.9v 150 a nrst, sdata, clk_sel, sclk v cccs = v in = 3.465v or 2.625v or 1.9v 5 a i il input low current pll_byp, ? sa1, oe1, oe0 v cccs = 3.465v or 2.625v or 1.9v, v in = 0v -5 a nrst, sdata, clk_sel, sclk v cccs = 3.465v or 2.625v or 1.9v, v in = 0v -150 a v oh output high voltage los, lock, ? sdata, 1 sclk note 1. use of external pull-up resistor is recommended. v cccs = 3.3v 5%, i oh = -2ma 2.6 v los, lock, ? sdata, 1 sclk v cccs = 2.5v 5%, i oh = -2ma 1.8 v ref_out 2 note 2. ref_out is intern ally regulated 1.8v output. i oh = -2ma 1.45 v v ol output low voltage los, lock, ? sdata 1 , sclk v cccs = 3.3v 5% or 2.5v 5%, i ol = 2ma 0.4 v ref_out 2 i ol = 2ma 0.45 v table 9b. differential input dc characteristics, v cca = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk v cca = v in = 3.465v or 2.625v 150 a i il input low current clk v cca = 3.465v or 2.625v, v in = 0v -5 a nclk v cca = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 1 note 1. v il should not be less than -0.3v. v ih should not be higher than v cca. 0.15 1.3 v v cmr common mode input voltage 1, 2 note 2. common mode voltage is defined as the cross-point. v ee v cca ? 1.2 v
29 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 9c. lvpecl dc characteri stics, v ccox 1 = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1. v ccox denotes: v cco0 through v cco8, v cco10. symbol parameter test conditions v ccox 1 = 3.3v5% v ccox 1 = 2.5v5% units minimum typical maximum minimum typical maximum v oh output ? high voltage 2 note 2. outputs terminated with 50 ? to v ccox ? 2v. v ccox - 1.3 v ccox - 0.8 v ccox - 1.4 v ccox - 0.9 v v ol output ? low voltage 2 v ccox - 1.95 v ccox - 1.75 v ccox - 1.95 v ccox - 1.75 v table 9d. lvds dc characteristics, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5% or 2.5v 5%, v ee = 0v, ? t a = -40c to 85c 3 note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. note 3. terminated 100 ? across qx and nqx. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 195 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.375 v ? v os v os magnitude change 50 mv table 9e. lvcmos clock output dc characteristics, v ccx 1 = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c 2 note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. symbol parameter test conditio ns minimum typical maximum units v oh output ? high voltage qx, nqx v ccox = 3.3v5%, i oh = -8ma 2.6 v v ol output ? low voltage qx, nqx v ccox = 3.3v5%, i ol = 8ma 0.4 v v oh output ? high voltage qx, nqx v ccox = 2.5v5%, i oh = -8ma 1.8 v v ol output ? low voltage qx, nqx v ccox = 2.5v5%, i ol = 8ma 0.4 v v oh output ? high voltage qx, nqx v ccox = 1.8v5%, i oh = -2ma v ccox ? 0.45 v v ol output ? low voltage qx, nqx v ccox = 1.8v5%, i ol = 2ma 0.45 v
30 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 10. input frequency characteristics, v ccx = 3.3v5% or 2.5v5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units f in input frequency 1 note 1. for the input reference frequency, the divider values must be set for the vco to operate within its supported range. osci, osco using a crystal (see table 11, crystal characteristics ) 10 40 mhz overdriving crystal input, doubler logic enabled 2 note 2. for optimal noise performance, the us e of a quartz crystal is recommended. refer to overdriving the xtal interface in the applica- tions information section. 10 62.5 mhz overdriving crystal input, doubler logic disabled 2 10 125 mhz clk, nclk 10 600 mhz f sclk serial port clock sclk (slave mode) i 2 c operation 100 400 khz table 11. crystal characteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 15 ? load capacitance (c l ) 12 pf frequency stability (total) -100 100 ppm
31 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet ac electrical characteristics table 12a. ac characteristics, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 3 symbol parameter test conditio ns minimum typical maximum units f vco vco operating frequency 3000 4000 mhz f ref pll input reference frequency 10 150 mhz f out output frequency lvpecl, lvds, hcsl q[8:11], nq[8:11] integer divider 0.008 1000 mhz q[0:7], nq[0:7] integer output dividers with no skew adjustment 0.008 666.67 mhz q[0:7], nq[0:7] outputs fractional divide and/or added skew delay 0.008 400 mhz lvcmos q[0:11], nq[0:11] 0.008 250 mhz ref_out 10 250 mhz t r / t f output ? rise and fall times lvpecl 20% to 80%, f out < 666mhz 250 650 ps 20% to 80%, f out ? 666mhz 180 450 ps lvds 20% to 80% 100 460 ps hcsl 20% to 80% 130 600 ps lvcmos 4 , 5 q[0:11], nq[0:11] 20% to 80%, v ccox = 3.3v 160 630 ps q[0:11], nq[0:11] 20% to 80%, v ccox = 2.5v 160 620 ps q[0:11], nq[0:11] 20% to 80%, v ccox = 1.8v 190 700 ps ref_out 20% to 80% 210 740 ps sr output ? slew rate 6 lvpecl measured on differential waveform, 150mv from center 14v/ns lvds measured on differential waveform, 150mv from center 0.5 4 v/ns hcsl measured on differential waveform, 150mv from center, v ccox = 2.5v, f out ? 125mhz 1.5 4 v/ns measured on differential waveform, 150mv from center, v ccox = 3.3v, f out ? 125mhz 2.5 5.5 v/ns t sk(b) bank skew 7 lvpecl q8, nq8; q9, nq9 8, 9, 10 75 ps q10, nq10; q11, nq11 8, 9, 10 75 ps lvds q8, nq8; q9, nq9 8, 9, 10 75 ps q10, nq10; q11, nq11 8, 9, 10 75 ps hcsl q8, nq8; q9, nq9 8, 9, 10 75 ps q10, nq10; q11, nq11 8, 9, 10 75 ps lvcmos q8, nq8; q9, nq9 4, 8, 9, 11 115 ps q10, nq10; q11, nq11 4, 8, 9, 11 115 ps
32 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet odc output ? duty cycle 12 lvpecl, lvds, hcsl f out ? 666.667mhz 45 50 55 % f out > 666.667mhz 40 50 60 % lvcmos q[0:11], nq[0:11] 40 50 60 % ref_out f out ? 62.5mhz 13 40 60 % ? ssb (1k) single sideband ? phase noise 14 1khz 122.88mhz output -113 dbc/ hz ? ssb (10k) 10khz 122.88mhz output -130 dbc/ hz ? ssb (100k) 100khz 122.88mhz output -137 dbc/ hz ? ssb (1m) 1mhz 122.88mhz output -149 dbc/ hz ? ssb (10m) 10mhz 122.88mhz output -155 dbc/ hz ? ssb (30m) ? 30mhz 122.88mhz output -156 dbc/ hz spurious limit at offset ? 800khz 122.88mhz output 15 -85 dbc t startup startup time internal otp startup 16 from v ccx >80% to first output clock edge 110 150 ms external eeprom startup 16 , 17 i 2 c frequency = 100khz; from v ccx >80% to first output clock edge (0 retries) 150 200 ms i 2 c frequency = 400khz; from v ccx >80% to first output clock edge (0 retries) 130 150 ms i 2 c frequency = 100khz; from v ccx >80% to first output clock edge (31 retries) 925 1200 ms i 2 c frequency = 400khz; from v ccx >80% to first output clock edge (31 retries) 360 500 ms note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. note 3. electrical parameters are guaran teed over the specified ambient operating tem perature range, which is established when the device is mounted in a test socket with ma intained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 4. appropriate se_mode bit must be configured to select phase-aligned or phase-inverted operation. note 5. all q and nq outputs in phase-inverted operation. note 6. measured from -150mv to +150mv on the differential wave form (derived from qx minus nq x). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is cent ered on the differential zero ? crosspoint. note 7. defined as skew within a bank of outputs at the same voltages and with equal load conditions. note 8. this parameter is guaranteed by characterization. not tested in production. note 9. this parameter is defined in accordance with jedec standard 65. note 10. measured at the outp ut differential crosspoints. note 11. measured at v ccox /2 of the rising edge. all qx and nqx outputs phase-aligned. note 12. duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device. table 12a. ac characteristics, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 3 (continued) symbol parameter test conditio ns minimum typical maximum units
33 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet note 13. ref_out output duty cycle characterized with clk input duty cycle between 48% and 52%. note 14. both pll and output dividers are in integer mode. characterized with 8t49n1012-900. note 15. tested with all out puts operating at 122.88mhz. note 16. this parameter is guaranteed by design. note 17. assuming a clear i 2 c bus. table 12b. hcsl ac characteristics, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5% or 2.5v 5%, ? t a = -40c to 85c 3 note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. note 3. electrical parameters are guaranteed over the specifie d ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airf low greater than 500 lfpm. the device will meet specification s after thermal equilibrium has be en reached under these conditions. symbol parameter test conditions minimum typical maximum units v rb ring-back voltage margin 4 , 5 note 4. measurement taken from differential waveform. note 5. t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv differential range. -100 100 mv t stable time before v rb is allowed 4 , 5 500 ps v max absolute max. output voltage 6 , 7 note 6. measurement taken from single-ended waveform. note 7. defined as the maximum instantaneous voltage including overshoot. 1150 mv v min absolute min. output voltage 6 , 8 note 8. defined as the minimum inst antaneous voltage including undershoot. -300 mv v cross absolute crossing voltage 9 , 10 note 9. measured at crossing point where the instantaneous voltage value of the rising edge of qn equals the falling edge of nq n. note 10. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. ref ers to all crossing points for this measurement. 250 550 mv ? v cross total variation of v cross over all edges 9 , 11 note 11. defined as the total variation of all crossing voltages of rising qn and falling nqn. this is the maximum allowed vari ance in v cross for any particular system. 140 mv
34 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet table 13. typical rms phase jitter, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 3 note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. note 3. all outputs configured for the sp ecific output type, as shown in the table. symbol parameter test condit ions lvpecl lvds hcsl lvcmos 4 note 4. qx and nqx are 180 out of phase. units tjit( ? ) rms ? phase jitter 5 (random) integration range: 12khz - 20mhz note 5. it is recommended to use idt?s timing commander software to program the device for optimal jitter performance. q[0:7] integer f out = 122.88mhz 6 note 6. characterized with 8t49n1012-900. 219 218 216 238 fs f out = 156.25mhz 7 note 7. characterized with 8t49n1012-901. 223 220 223 220 fs f out = 622.08mhz 8 note 8. characterized with 8t49n1012-902. 183 190 199 n/a 9 note 9. this frequency is not supported for lvcmos operation. fs q[8:11] f out = 122.88mhz 6 251 251 240 263 fs q[0:7] fractional f out = 122.88mhz 10 note 10. characterized with 8t49n1012-903. 295 296 294 307 fs table 14. pci express jitter specifications, v ccx 1 = 3.3v 5% or 2.5v 5%, v ccox 2 = 3.3v 5% or 2.5v 5%, ? t a = -40c to 85c 3 note 1. v ccx denotes: v ccd, v cc, v cccs. note 2. v ccox denotes: v cco0 through v cco8, v cco10. note 3. electrical parameters are guaranteed over the specifie d ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airf low greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum pcie industry specification units tj (pcie gen 1) phase jitter peak-to-peak 4 , 5 , 6 note 4. peak-to-peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci ex press gen1. note 5. this parameter is guaranteed by characterization. not tested in production. note 6. outputs configured for hscl mode using integer output dividers. fox 277lf-40-22 (40mhz , 12pf) crystal used with doubler logic enabled. ? = 100mhz, 40mhz crystal input, evaluation band: 0hz - nyquist (clock frequency/2) 618 86ps t refclk_hf_rms (pcie gen 2) phase jitter rms 5 , 6 , 7 note 7. rms jitter after applying the two evaluation bands to th e two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t ref- clk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). ? = 100mhz, 40mhz crystal input, high band: 1.5mhz - nyquist (clock frequency/2) 0.5 1.8 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms 5 , 6 , 7 ? = 100mhz, 40mhz crystal input, low band: 10khz - 1.5mhz 0.1 0.5 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms 5 , 6 , 8 note 8. rms jitter after applying system transfer function for the common clock architecture. this specification is based on th e pci ex- press base specification revision 0.7, october 2009 and is subj ect to change pending the final release version of the specifica - tion. ? = 100mhz, 40mhz crystal input, evaluation band: 0hz - nyquist (clock frequency/2) 0.1 0.2 0.8 ps
35 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet typical phase noise at 122.88mhz (3.3v) noise power dbc ? hz offset frequency (hz)
36 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet applications information overdriving the xtal interface the osci input can be overdriven by an lvcmos driver or by one side of a differential driver thr ough an ac coupling capacitor. the osco pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcm os inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 5a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this co n figuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will a ttenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 : applications, r1 and r2 can be 100 : . this can also be accomplished by removing r1 and changing r2 to 50 : . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 5b shows an example of the in terface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the osci input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, th ey can be utilized for debugging purposes. if the duty cycle of the input reference is not 50% then increased phase noise may result. the datasheet spec ifications are characterized and guaranteed by using a quartz crystal as the input. lvcmos_driver zo = 50 rs zo = ro + rs ro r2 100 r1 100 vcc osco osci c1 0.1f fiure 5a. enerl dir or lvcmos driver to tal input interce fiure 5. enerl dir or lvpec l driver to tal input interce lvpecl_driver zo = 50 r2 50 r3 50 c2 0.1f osco osci zo = 50 r1 50
37 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet wiring the differential input to accept single-ended levels figure 6 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v ccd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bi as circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v ccd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. similarly, if the input clock swing is 1.8v and v ccd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 0.9v. it is recommended to always use r1 and r2 to provide a known v 1 voltage. the values below are for when both the single ended swing and v ccd are at the same voltage. this configuration requir es that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 : applications, r3 and r4 can be 100 : . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v ccd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 6. recommended schematic for wiring a di fferential input to accept single-ended levels
38 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 3.3v differential cl ock input interface clk/nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 7a to figure 7e show interface examples for the clk/nclk input dr iven by the most common driver types. the input interfaces sugge sted here are examples only. please consult with the vendor of th e driver component to confirm the driver termination requirem ents. for example, in figure 7a , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from anot her vendor, use their termination recommendation. figure 7a. clk/nclk input driven by an ? idt open emitter lvhstl driver figure 7b. clk/nclk input driven by a ? 3.3v lvpecl driver figure 7c. clk/nclk input driven by a ? 3.3v hcsl driver figure 7d. clk/nclk input driven by a ? 3.3v lvpecl driver figure 7e. clk/nclk input driven by a ? 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input
39 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 2.5v differential cl ock input interface clk/nclk accepts lvds, lvpecl, lvhstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 8a to figure 8d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 8a , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from anot her vendor, use their termination recommendation. figure 8a. clk/nclk input driven by an ? idt open emitter lvhstl driver figure 8b. clk/nclk input driven by a ? 2.5v lvpecl driver figure 8c. clk/nclk input driven by a ? 2.5v lvpecl driver figure 8d. clk/nclk input driven by a ? 2.5v lvds driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 2.5v lvhstl idt open emitter lvhstl driver differential input
40 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet recommendations for unused input and output pins i nputs: clk/nclk inputs for applications not requiring the use the reference clock inputs, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. it is recommended that clk, nclk not be driven with active signals when not enabled for use by the pll. crystal inputs for applications not requiring the us e of the crystal oscillator input, both osci and osco can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from osci to ground. lvcmos control pins all control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: differential outputs unused differential outputs should be programmed to high-impedance. lvcmos outputs if only one output from an output pair (such as q0 is used and nq0 remains unused) is intended for use, it is then recommended to program the unused output to inverted mode and terminate both outputs properly. if both outputs (qx and nqx) are unused, it is recommended to program the output buffers to high-impedance.
41 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 : and 132 : . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical poi nt-to-point lvds design uses a 100 : parallel resistor at the receiver and a 100 : differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 9a can be used with either type of output structure. figure 9b , which can also be used with both output type s, is an optional te rmination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds driver z o | z t z t lvds receiver figure 9a.standard lvds termination lvds driver z o | z t lvds receiver c z t 2 z t 2 figure 9b. optional lvds termination
42 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (d c current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 10a and figure 10b show two different layouts which are recomm ended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to g uarantee compatibility across all printed circuit and clock component process variations. figure 10a. 3.3v l vpecl output termination figure 10b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v + _
43 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet termination for 2.5v lvpecl outputs figure 11a and figure 11c show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 11c can be eliminated and the termination is shown in figure 11b . figure 11a. 2.5v lvpecl driver termination example figure 11b. 2.5v lvpecl driver termination example figure 11c. 2.5v lvpecl driver termination example 2.5v lvpecl driver v ddo = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v ddo = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v ddo = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
44 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 2.5v and 3.3v hcsl output termination figure 12a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 12a. recommended source termination (where th e driver and receiver will be on separate pcbs) figure 12b is the recommended termination for applications where a point-to-point connection can be us ed. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unw anted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 12b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
45 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 13 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further informatio n, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 13. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) schematic and la yout information schematics for 8t49n1012 can be found on idt.com. please search for the 8t49n1012 device and click on the link for evaluation board schematics. crystal recommendation this device was characterized usin g fox 277lf series through-hole crystals including part #277lf-40-18 (40mhz) and 277lf-38.88-2 (38.88mhz). if a surface mount cryst al is desired, we recommend fox part #603-40-48 (40mhz) or fox part #603-38.88-7 (38.88mhz). i 2 c serial eeprom recommendation the 8t49n1012 was designed to operate with most standard i 2 c serial eeproms of 256 bytes or larger. atmel at 24c04c was used during device characterization and is recommended for use. please contact idt for review of any other i 2 c eeprom?s compatibility with the 8t49n1012. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
46 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet pci express application note pci express jitter analysis methodology models the system response to reference clock jitt er. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (t x) and receive (rx) serdes plls are modeled as well as the phase inte rpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: ht s h3 s h1 s h2 s ? >@ u = the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: ys xs h3 s u h1 s h2 s ? >@ u = in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci ex press gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note, pci express application note .
47 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet power dissipation and thermal considerations the 8t49n1012 is a multi-functional, high s peed device that targets a wide variety of clock frequencies and applications. since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. the 8t49n1012 device was designed and characterized to operate wi th in the ambient industrial tem perature range of -40c to +85 c. the ambient temperature represents the temperat ure around the device, not the junction te mperature. when using the device in extrem e cases, such as maximum operating frequency and high ambient temperature, external air flow ma y be required in order to ensure a safe and reliable junction temperature. extreme care must be ta ken to avoid exceeding 125c junction temperature. the power calculation examples below were generated using a ma xi mum ambient temperature and supply voltage. for many applicatio ns, the power consumption will be much lower. please contact idt technica l support for any concerns on calculating the power dissipatio n for your own specific configuration. power domains the 8t49n1012 device has a number of separate power domains that can be independently enabled and disabled via register accesse s (all power supply pins must still be connected to a valid supply voltage). figure 14 below indicates the individual domains and the associated power pins. control & status buffers (v cccs ) los, lock, nrst, sa1, sdata, sclk, clk_sel, oe[1:0], pll_byp, ref_out core digital logic (v ccd ) core memory (v cc ) otp memory core analog circuitry (v cca ) clk, nclk, oscillator and pll q1 output buffer & mux, div b (v cco1 ) q0 output buffer & mux, div a (v cco0 ) q2 output buffer & mux, div c (v cco2 ) q3 output buffer & mux, div d (v cco3 ) q4 output buffer & mux, div e (v cco4 ) q5 output buffer & mux, div f (v cco5 ) q6 output buffer & mux, div g (v cco6 ) q7 output buffer & mux, div h (v cco7 ) q8 & q9 output buffers & mux, div i (v cco8 ) q10 & q11 output buffers & mux, div j (v cco10 ) figure 14. 8t49n1012 power domains for the output paths shown above, there are many different structures that are used. po wer consumption data will vary slightly depending on the structure used as shown in the output curr ent calculation tables on the following pages.
48 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet power consumption calculation determining total power consumption involves several steps: 1. determine the power consumption using maximum current values for core and analog voltage supplies from table 8a through table 8b . 2. determine the nominal power consumption of each enabled output path. a. this consists of a base amount of power that is independent of operating frequency, as shown in table 16a through table 16g (depending on the chosen output protocol). b. then there is a variable amount of power that is related to the ou tput frequency. this can be determined by multiplying the output frequency by the fq_factor shown in table 16a through table 16g . 3. all of the above totals are then summed. thermal considerations once the total power consumption has been determined, it is nece ssary to calculate the maximum operating junction temperature f or the device under the environmental conditions it will operate in. thermal conduction paths, air fl ow rate and ambient air temperature are factors that can affect this. the thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via cond uction into the pcb through the device pads (including the epad). therma l conduction data is provided for typical scenarios in table 15 below. please contact idt for assistance in calculating results under other scenarios. table 15. thermal resistance ? ja for 72-lead vfqfn, forced convection ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 16.1c/w 12.4c/w 11.1c/w
49 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet current consumption data and equations table 16a. 3.3v lvpecl/hcsl output current calculation table table 16b. 3.3v lvds output current calculation table table 16c. 3.3v lvcmos output current calculation table table 16d. 2.5v lvpecl/ hcsl output current calculation table table 16e. 2.5v lvds output current calculation table table 16f. 2.5v lvcmos output current calculation table table 16g. 1.8v lvcmos output current calculation table lvpecl/hcsl fq_factor (a/ mhz) base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and an output pair. 15.0 43.2 q[8:9], q[10:11] 2 note 2. the values are based on a divider and two output pairs. 16.4 34.7 lvds fq_factor (a/mhz) base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and an output pair. 15.0 52.6 q[8:9]], q[10:11] 2 note 2. the values are based on a divider and two output pairs. 16.4 52.5 lvcmos base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and two ? lvcmos outputs). 41.2 q[8:9], q[10:11] 2 note 2. the values are based on a divider and four lvcmos outputs. 30.5 lvpecl/hcsl fq_factor ( a/mhz) base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and an output pair. 12.0 41.9 q[8:9], q[10:11] 2 note 2. the values are based on a divider and two output pairs. 11.5 32.0 lvds fq_factor (a/mhz) base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and an output pair. 12.0 50.6 q[8:9], q[10:11] 2 note 2. the values are based on a divider and two output pairs. 11.5 48.9 lvcmos base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and two ? lvcmos outputs). 40.2 q[8:9], q[10:11] 2 note 2. the values are based on a divider and four lvcmos outputs 28.7 lvcmos base_current (ma) q[0:7] 1 note 1. the values are per channel (one divider and two ? lvcmos outputs). 39.7 q[8:9], q[10:11] 2 note 2. the values are based on a divider and four lvcmos outputs 27.5
50 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet applying the values to the following equat ion will yield output current by frequency: qx current = fq_factor * frequency + base_current where: qx current is the specific output current a ccording to output type and frequency fq_factor is used for calculating current increase due to output frequency base_current is the base current for each output path independent of output frequency the second step is to multiply the power dissipated by the the rmal impedance to determine the maximum power gradient, using the following equation: t j = t a + ( ? ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) ? ja is the thermal resistance value from table 15 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8t49n1012 under usage conditions, including power dissipated due to loading (w). note that the power dissipation per output pair due to loading is assumed to be 27.95mw for lvpecl outputs and 44.5mw for hcsl outputs. when selecting lvcmos outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. for these examples, power dissipation through loading will be calculated using c pd (found in table 2 ) and output frequency: pd out = c pd * f out * v cco 2 where: pd out is the power dissipation of the output (w) c pd is the power dissipation capacitance (f) f out is the output frequency of the selected output (hz) v cco is the voltage supplied to the appropriate output (v)
51 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet example calculations example 1. pll is running in integer mode and ref_out off (3.3v core voltage) output output type frequency (mhz) v cco q0 lvcmos 25 1.8 q1 lvcmos 125 3.3 q2 lvpecl 25 3.3 q3 hcsl 100 3.3 q4 lvpecl 100 3.3 q5 lvpecl 100 3.3 q6 lvcmos 100 2.5 q7 lvds 100 3.3 q8 lvpecl 100 3.3 q9 lvpecl 100 3.3 q10 lvds 150 2.5 q11 lvds 150 2.5 core power dissipation: ? core supply current, i cc = 28ma (v ccd = v cc = v cccs = 3.3v) ? analog supply current, i cca = 170ma (v cca = 3.3v) ? total core and analog power = 3.465v * (28 + 170)ma = 68 6.1mw output power dissipation: q0 current = 15pf * 25mhz * 1.89v + 39.7ma = 40.4ma q1 current = 17pf * 125mhz * 3.465v + 41.2ma = 48.6ma q2 current = 15a/mhz * 25mhz + 43.2ma = 43.6ma q3 current = 15a/mhz * 100mhz + 43.2ma = 44.7ma q4 current = 15a/mhz * 100mhz + 43.2ma = 44.7ma q5 current = 15a/mhz * 100mhz + 43.2ma = 44.7ma q6 current = 15pf * 100mhz * 2.5v + 40.2ma = 44ma q7 current = 15a/mhz * 100mhz + 52.6ma = 54.1ma q[8:9] current = 16.4a/mhz * 100mhz + 34.7ma = 36.3ma q[10:11] current = 11.5a/mhz * 150mhz + 48.9ma = 50.6ma ? output current @ 1.8v = 40.4ma ? output current @ 2.5v = 44ma + 50.6ma = 94 .6ma ? output current @ 3.3v = 48.6ma + 43.6ma + 44 .7 ma + 44.7ma + 44.7ma + 54.1ma + 36.3ma = 316.7ma ? power dissipated due to switching: lvpecl outputs = 5 * 27.95mw = 13 9.8mw hcsl output = 1 * 44.5mw = 44 .5mw total output power = (1.89v * 40.4 ma ) + (2.625v * 94.6ma) + (3.465v * 316.7ma) + 139.8mw + 44.5mw = 1606.35mw total power dissipation: ? total power = 686.1mw + 1606.35mw = 22 92.4mw junction temperature calculation: with an ambient temperature of 85c and no airflow, the junc tion temperature is: t j = 85c + 16.1c/w * 2.2924w = 121.9c (which is below the maximum allowable temperature) due to the 8t49n1012 flexibility and highly con figurable outputs, the power dissipation will vary depending on the specific dev ice configuration. the power calculations example shown above illustrates a single configuration and its correspond ing power figures. if additiona l support on calculating power consumption for other configurations is needed, please contact idt (clocks@idt.com).
52 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet reliability information table 17. ? ja vs. air flow table for a 72-lead vfqfn note: theta ja ( ? ja )values calculated using a 4-layer jedec pcb (114.3mm x 101.6mm), with 2oz. (70um) copper plating on all 4 layers. transistor count the transistor count for 8t49n1012 is: 579,607 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 16.1c/w 12.4c/w 11.1c/w
53 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 72-lead vfqfn package outline i www.idt.com dt
54 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 72-lead vfqfn package outline, continued i www.idt.com dt
55 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet 72-lead vfqfn package outline, continued i www.idt.com dt
56 ?2016 integrated device technology, inc. october 28, 2016 8t49n1012 datasheet ordering information table 18. ordering information note: for the specific, publicly ava ilable -ddd order codes, refer to femtoclock ng universal frequency translator ordering product information document. for custom -ddd order codes, please contact idt for more information. table 19. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 8t49n1012-dddnlgi idt8t49n1012-dddnlgi 72-lead vfqfn, lead-free tray -40 ? c to +85 ? c 8t49n1012-dddnlgi8 idt8t49n1012-dddnlgi 72-lead vfqfn, lead-free tape & reel, pin 1 orientation: eia-481-c -40 ? c to +85 ? c 8t49n1012-dddnlgi# idt8t49n1012-dddnlgi 72-lead vfqfn, lead-free tape & reel, pin 1 orientation: eia-481-d -40 ? c to +85 ? c part number suffix pin 1 orientation illustration nlgi8 quadrant 1 (eia-481-c) nlgi# quadrant 2 (eia-481-d) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes)
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8t49n1012 datasheet revision history sheet date description of change october 28, 2016 crystal recommendation - deleted idt crystal reference.

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